This application claims benefit of priority under 35 USC xc2xa7119 to Japanese patent application No.2000-115120, filed on Apr. 17, 2000, the contents of which are incorporated by reference herein.
1. Field of The Invention
The present invention relates generally to a semiconductor device. More specifically, the invention relates to the structure of a semiconductor device which has an improved integration degree by improving the planarization of the device and the alignment precision during the production thereof.
2. Related Background Art
In order to scale down semiconductor devices, it is important to flatten the surfaces of semiconductor wafers and to improve the alignment precision between fabricating steps.
For example, as shown in FIG. 6A, if an underlayer 101, on which a pattern is to be transferred, has a difference in level at a lithography step for fabricating a semiconductor device, a resist film 105 also has a difference in level, so that the focal position of exposure beams LB for transferring a pattern fluctuates. For example, if the focal position of exposure beams LB is matched with the portion having the difference in level, a normal pattern image Img1 can be obtained thereon. However, the focal position is shifted on a flat portion so as not to normally form an image thereon, so that a transferred pattern image Img2xe2x80x2 is a pattern image which is out of focus. For that reason, if an underlayer pattern has a large number of differences in level, a fine pattern can not be transferred. Therefore, in order to obtain normal pattern images in all of regions to be transferred, it is necessary to flatten an underlayer pattern 103 as flat as possible as shown in, e.g., FIG. 6B before the lithography step.
As planarization techniques, the chemical mechanical polishing (which will be hereinafter referred to as the xe2x80x9cCMPxe2x80x9d) technique is widely used in recent years. The CMP is a technique for applying a fine abrasive material on the surface of a wafer to mechanically polish the surface thereof.
However, in the polishing using the CMP, it is required to lubricatively supply the abrasive material between a smooth polishing plate and the surface of the wafer and to rapidly discharge polished waste materials from the surface of the wafer after the polishing. Therefore, when a large pattern is polished or when polishing is carried out in a wide area between patterns, the adhesion between the polishing plate and the surface of the wafer is too high, so that the supply of the abrasive material and the discharge of the polished waste materials are obstructed. For that reason, it is difficult to carry out a good polishing. In addition, if a pattern, only a small part of which has a protruding portion, is polished, the polishing force concentrates on the protruding pattern, so that the polishing rate remarkably increases, thereby being difficult to control the quantity of polished materials. For that reason, in order to improve the polishing precision using the CMP, the maximum size of a pattern to be polished and the ratio of irregularities must be appropriately set.
Therefore, it is important to closely arrange patterns while adjusting the ratio of irregularities of the patterns.
FIGS. 7A and 7B are schematic sectional views for explaining the need for closely arranging patterns on the surface of a wafer. As shown in FIG. 7A, when only one transistor is intended to be formed, only a transistor forming pattern PT1 protrudes with respect to a surrounding wide element isolating region 110. However, as shown in FIG. 7B, if a pattern PT2 is arranged so as to be close to the pattern PT1 the ratio of protruding portions in the surface region, so that it is possible to set an appropriate quantity for processing.
A conventional aligning method between fabricating steps will be described below.
FIG. 8A is an illustration for explaining a conventional aligning method. Furthermore, in the following drawings, the same reference numbers are given to the same portions, and the detailed descriptions thereof are omitted.
An alignment mark 50 includes three linear patterns Pa1 through Pa3 which are arranged in parallel to each other. With respect to these linear patterns, an optical image using an optical microscope or an electron diffraction image using a scanning electron microscope is acquired in a range extending perpendicularly to the respective lines as shown in a region Rp50, to obtain light intensities or electron beam intensities, a profile of FIG. 8B is obtained. It can be seen from FIG. 8B that an intensity distribution corresponding to the arrangement of the respective patterns Pa1 through Pa3 is obtained. Defining the intensity peaks corresponding to the patterns Pa1 through Pa3 as Sa1 through Sa3, respectively, defining the distance between the patterns Sa3 and Sa1 as d1 and defining the distance between the patterns Sa3 and Sa3 as d2, these distances correspond to pitches between the respective patterns, respectively. When three lined-up peaks, the distances between which are d1 and d2 in order from the left in FIG. 8B, are observed, if it is previously registered in a pattern recognition system that the central peak is set as the origin in alignment, it is possible to carry out an alignment between the current step and the last step.
In order to carry out the CMP of a device including alignment marks shown in FIG. 8A, it is difficult to apply the CMP with respect to both of a too broad pattern and a too wide space, some pattern must be arranged around the alignment marks.
FIG. 9A shows an example of a semiconductor device in which patterns including such a CMP processing dummy pattern are arranged. The dummy pattern is arranged for the main purpose of improving the CMP processing precision, and plays little part in the operation of the device. Furthermore, in place of the dummy pattern, a pattern playing some part in the operation of the device may be arranged to enhance the CMP processing precision.
In a semiconductor device shown in FIG. 9A, dummy patterns Pd are arranged from a position, which is spaced from the line patterns Pa1 in an alignment mark 60 by a distance d2, in a region Rc60 having an appropriate set size, and periodically arranged in a cycle d1 in lateral directions of the figure.
If the light intensity or electron beam intensity of the patterns is derived in the same manner as the method shown in FIG. 8B, a profile of FIG. 9B is obtained. A combination of three lined-up peaks, the distances between which are d1 and d2 in order from the left of the figure, is extracted from a profile of FIG. 9B, it is possible to fine two combinations, i.e., a combination SET1 based on the original alignment mark 60, and a combination SET2 based on the dummy patterns and a part of the alignment mark 60. This shows that there is some possibility that the origin is set at an erroneous place, such as the SET2, if the alignment is carried out using the pattern arrangement shown in FIG. 9A. This causes a problem in that the alignment precision is remarkably deteriorated.
Although false recognition from the surrounding dummy patterns can be prevented if the alignment marks are further complicated, the recognizing procedure is more complicated than the procedure for identifying the alignment mark itself, so that the costs of the identifying system are increased and the alignment rate is decreased, thereby increasing the whole manufacturing costs.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor device capable of improving an alignment precision while further developing the scale down of a device by flattening the device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: first patterns for alignment which are arranged in a first region on the surface of a semiconductor substrate, the first patterns including (n+1) first patterns (n is a natural number) in at least a first direction; and second patterns which are formed in a second region on the surface of the semiconductor substrate, the second region extending outwardly from the first region in the first direction, the second patterns including a plurality of patterns in a period of dD in at least the first direction, wherein defining a size of a pitch between adjacent two of the first patterns in the first direction as dk (1xe2x89xa6kxe2x89xa6n), defining a coefficient depending on a precision in pattern recognition in the first direction as xcex1 (1 greater than xcex1 greater than 0), and defining a distance between one of the first pattern which is closest to the second region in the first direction and the outside edge of the second region as D, the second region is set so as to satisfy the following relational expression,   D  ≦            ∑              k        =        1            n        ⁢    dk  
and the dD is set so as to satisfy the following relational expression with respect to optional dk.
|(dDxe2x88x92dk)/dk|xe2x89xa7xcex1
According to the semiconductor device, the period dD of the second patterns is set so as to be shifted from each pitch between the first patterns by a predetermined margin, so that it is possible to prevent patterns other than an alignment mark from being erroneously recognized as the alignment mark in the pattern recognition for alignment between fabricating steps while giving the density of irregularities suitable for the CMP processing or the like to the surface of a wafer. Thus, according to the present invention, it is possible to improve the alignment precision between fabricating steps while advancing the scale down of a semiconductor device due to the planarization of the device.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: first patterns for alignment which are arranged in a first region on the surface of a semiconductor substrate, the first patterns including (n+1) first patterns (n is a natural number) in at least a first direction; and second patterns which are formed in a second region on the surface of the semiconductor substrate, the second region extending outwardly from the first region in the first direction, the second patterns including m second patterns (m is a natural number) which are non-periodically arranged in at least the first direction, wherein defining a size of a first pitch between adjacent two of the first patterns in the first direction as dk (1xe2x89xa6kxe2x89xa6n), defining a second pitch between one of the first patterns and one of the second patterns, which are closest to each other between the first region and the second region, in the first direction as dm, defining a size of a third pitch between adjacent two of the second patterns in the first direction as d(m-1) when mxe2x89xa72, defining a coefficient depending on a precision in pattern recognition as xcex1 (1 greater than xcex1 greater than 0), and defining a distance between one of the first pattern, which is closest to the second region in the first direction, and the outside edge of the second region as D, the second region is set so as to satisfy the following relational expression,   D  ≦            ∑              k        =        1            n        ⁢    dk  
and the dm is set so as to satisfy the following relational expression with respect to a combination of the dm with optional dk.
|(dmxe2x88x92dk)/dk|xe2x89xa7xcex1
According to the second aspect of the present invention, any pitches between the second patterns are set so as to be shifted from each pitch between the first patterns by a predetermined margin, so that it is possible to prevent patterns other than the alignment mark from being erroneously recognized as the alignment mark in the pattern recognition for alignment even if the second patterns are non-periodic patterns. Thus, it is possible to improve the alignment precision between fabricating steps while advancing the scale down of a semiconductor device due to the planarization of the device.
The second patterns may be line patterns continuously arranged in a second direction perpendicular to the first direction.
In the first and second aspect of the invention, the semiconductor device may preferably further comprise third patterns arranged in a third region on the surface of the semiconductor substrate, the third region extending outwardly from the second region in the first direction, and the third patterns including patterns formed at a different pitch from that between the second patterns in at least the first direction and having a different shape from that of the second patterns.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: first patterns for alignment which are arranged in a first region on the surface of a semiconductor substrate, the first patterns including (n+1) first patterns (n is a natural number) in at least a first direction; and second patterns which are formed in a second region on the surface of the semiconductor substrate and which are linear patterns arranged continuously in the first direction, the second region extending outwardly from the first region in the first direction, wherein defining a size of a pitch between adjacent two of the first patterns in the first direction as dk (1xe2x89xa6kxe2x89xa6n), and defining the size of the second pattern in the first direction as S,
the second region is set so as to satisfy the following relational expression.   S  ≧            ∑              k        =        1            n        ⁢    dk  
According to the third aspect of the present invention, continuous patterns having no period in the first direction in the second region are arranged, so that it is possible to prevent patterns other than the alignment mark from being erroneously recognized as the alignment mark in the pattern recognition for alignment between fabricating steps while giving the density of irregularities suitable for the CMP processing to the surface of a wafer. Thus, it is possible to improve the alignment precision between fabricating steps while advancing the scale down of a semiconductor device due to the planarization of the device.
It is preferable in the third aspect of the invention, the semiconductor device further comprises third patterns which includes a plurality of patterns formed in at least the first direction in a third region on the surface of the semiconductor substrate, the third region extending outwardly from the second region in the first direction, the third patterns being arranged at a different pitch from a pitch between one of the first patterns and one of the third patterns, which are closest to each other between the first region and the third region, in the first direction, and the third patterns having a different shape from that of the second patterns.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising: first patterns for alignment which are arranged in a first region on the surface of a semiconductor substrate, the first patterns including (n+1) first patterns (n is a natural number) in at least a first direction; and second patterns which are arranged in a second region on the surface of the semiconductor substrate, the second region extending outwardly from the first region in the first direction, the second patterns including at least m pattern groups (m is a natural number) arranged repeatedly in at least the first direction, each of the pattern group being constituted with a unit of a combination of third patterns formed in a third region, the third region being included in the second region wherein defining a pitch between adjacent two of the first patterns in the first direction as dk (1xe2x89xa6kxe2x89xa6n), defining the size of the third region in the first direction as dD, defining a distance between one of the first patterns, which is closest to the second region in the first direction, and the outside edge of the second region as D, and defining a coefficient depending on a precision in pattern recognition in the first direction as xcex1 (1 greater than xcex1 greater than 0), the second region is set so as to satisfy the following relational expression,   D  ≦            ∑              k        =        1            n        ⁢    dk  
and the dD is set so as to satisfy the following relational expression with respect to optional dk.
|(dDxe2x88x92dk)/dk|xe2x89xa7xcex1
According to the fourth aspect of the present invention, even if pattern groups of complicated patterns are arranged in the second region, when these patterns are repeatedly arranged, defining the size of the third region, where the repeated units of pattern groups are formed in the first direction, as dD, this dD is set so as to be shifted from each pitch between the first patterns by a predetermined margin. Thus, it is possible to improve the alignment precision while giving the density of irregularities suitable for the CMP processing or the like to the surface of a wafer.
In the fourth aspect of the invention, it is preferable that the semiconductor device further comprises fourth patterns including a plurality of patterns arranged at a pitch, which is different from the dD, in at least the first direction in a fourth region on the surface of the semiconductor substrate, the fourth region extending outwardly from the second region in the first direction, and the fourth patterns having a different shape from those of the third patterns of the unit.
The first patterns may be rectangular patterns which are repeatedly formed periodically in a second direction perpendicular to the first direction or may be line patterns continuously arranged in a second direction perpendicular to the first direction.
Moreover, xcex1 is preferably 0.1.
The first direction means a recognizing direction when patterns are recognized using light beams or charged particle beams.
In the above described semiconductor device, the first patterns, the second patterns and the third patterns include both of element forming patterns and dummy patterns which do not participate in the formation of elements.
The size of the second patterns, the period of the second patterns in the second direction, and the spacing between the second patterns in the second direction may be suitably selected for the CMP processing.
Similarly, the size of the third patterns, the period of the third patterns in the second direction, and the spacing between the third patterns in the second direction may be suitably selected for the CMP processing.